DVCon U.S. Best Paper & Posters
The Best Paper and Poster is in honor of Stu Sutherland.
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2020 Recipients
Best Paper - 1st Place
5.3 UVM Reactive Stimulus Techniques Clifford E. Cummings - Sunburst Design, Inc., Heath Chambers - HMC Design Verification, Inc. & Sunburst Design, Inc., Stephen D’Onofrio - Paradigm Works, Inc. & Sunburst Design, Inc.
Best Paper - 2nd Place
5.1 UVM – Stop Hitting Your Brother Coding Guidelines Chris Spear, Rich Edelman - Mentor, A Siemens Business
Best Paper - 3rd Place
12.3 A SystemVerilog Framework for Efficient Randomization of Images With Complex Inter-Pixel Dependencies Gabriel Jönsson, Axel Voss, Lars Viklund - Axis Communications
Best Poster - 1st Place
4.1 SoC Firmware Debugging Tracer in Emulation Platform Kubendra Kumbar, Ken Joseph Kannampuzha - Samsung Semiconductor India R&D, Bangalore, Sandeep Vallabhaneni, Shim Hojun, Byung C. Yoo - Samsung Electronics Co., Ltd.
Best Poster - 2nd Place
4.14 Deadlock Verification For Dummies - The Easy Way Using SVA and Formal Mark Eslinger, Jeremy Levitt, Joe Hupcey III - Mentor, A Siemens Business
Best Poster - 3rd Place
4.15 Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros Brandon Skaggs - Cypress Semiconductor Corp.
2019 Recipients
Best Paper - 1st Place
7.3 Yikes! Why is My SystemVerilog Still So Slooooow? Clifford E. Cummings - Sunburst Design, Inc., John Rose, Adam Sherer - Cadence Design Systems, Inc.
Best Paper - 2nd Place
8.3 How to Test the Whole Firmware/Software when the RTL can’t fit the Emulator Horace Chan, Byron Watt - Microchip Technology, Inc.
Best Paper - 3rd Place
1.2 A Coverage-driven Formal Methodology for Verification Sign-off Hao Chen, Ang Li, Jason Yu, EeLoon Teoh, Iswerya Prem Anand - Intel Corp.
Best Poster - 1st Place
4.21 Emulation Testbench Optimizations for Better Hardware Software Co-Validation Vijayakrishnan Rousseau, Suresh Balasubramanian, Srikanth Reddy Rolla, Mohamed Saheel Nandikotkur Hussainsaheb - Intel Corp.
Best Poster - 2nd Place
4.20 Novel Approach to ASIC Prototyping Suresh Balasubramanian, Mohamed Saheel Nandikotkur Hussainsaheb, Vijayakrishnan Rousseau - Intel Corp.
Best Poster - 3rd Place
4.17 Verification Reuse for a Non-transaction Based Design Across Multiple Platforms Pablo Salazar, Luis Li, Andres Cordero - Hewlett Packard Enterprise
2018 Recipients
Best Paper - 1st Place
7.3 My Testbench Used to Break! Now it Bends: Adapting to Changing Design Configurations Jeffery Vance, Jeffrey Montesano, Kevin Vasconcellos, Kevin Johnston - Verilab, Inc.Download
Best Paper - 2nd Place
12.3 Error Injection in a Subsystem Level Constrained Random UVM Testbench Jeremy Ridgeway, Hoe Nguyen - Broadcom LimitedDownload
Best Paper - 3rd Place
6.1 Deep Predictive Coverage Collection Rajarshi Roy, Chinmay Duvedi, Saad Godil, Mark Williams - NVIDIA Corp.Download
Best Poster - 1st Place
4.18 Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages Timothy Pertuit, Doug Gibson, David Lacey - Hewlett Packard EnterpriseDownload
Best Poster - 2nd Place
4.16 Fast Track Formal Verification Signoff Mandar Munishwar - Qualcomm, Inc., Sandeep Jana - Synopsys (India) Pvt. Ltd., Xiaolin Chen, Arunava Saha - Synopsys, Inc.Download
Best Poster - 3rd Place
4.26 Tired of Slow Gate Level Design Verification? Use these Efficient Modelling Styles and Methodology Gabriel Chidolue, Rohit Jain, Shobana Sudhakar - Mentor, A Siemens BusinessDownload
2017 Recipients
Best Paper
7.2 Optimizing Random Test Constraints Using Machine Learning Algorithms Stan Sokorac - ARM, Inc.Download
Best Poster
4P.18 A New Approach for Generating View Generators Johannes Schreiner - Infineon TechnologiesDownload
Paper Honorable Mentions
7.1 Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation Eldon Nelson - Intel Corp.Download
10.1 Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification Honghuang Lin - Texas Instruments, Inc.Download
2016 Recipients
Best Paper
8.2 Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemsVerilog 1800-2012 Eldon G. Nelson - Intel Corp.Download
Best Poster
4P.32 Marrying Simulation and Formal Made Easier! Lun Li, Durga Rangarajan, Christopher Starr, James Green - Samsung Austin R&D Center; Nitin Mhaske - Synopsys, Inc.
Paper Honorable Mentions
9.3 Functional Coverage Collection for Analog Circuits - Enabling Seamless Collaboration Between Design and Verification Zhipeng Ye, Honghuang Lin, Asad Khan - Texas Insturments, Inc.Download
Poster Honorable Mentions
4P.22 Improving the UVM Register Model: Adding Product Feature Based API for Easier Test Programming Krishnan Balakrishnan, Courtney Fricano, Kaushal M. Modi - Analog Devices, Inc.Download
4P.14 How Do You Verify Your Verification Components Neil Johnson - XtremeEDA Corp.; Joshua W. Rensch - Superion TechnologyDownload